1. Field of the Invention
This invention relates to microprocessors, and more particularly, to translation lookaside buffers used for storing address translations.
2. Description of the Related Art
Many modem microprocessors support a form of virtual memory called “paging”. Paging enables system software to create separate address spaces for each process or application. Paging divides a physical address space, defined by the number of address signals generated by the processor, into fixed-sized blocks of contiguous memory called “pages”. If paging is enabled, a “virtual” address is translated or “mapped” to a physical address. Various mechanisms exist in different processor architectures for performing virtual-to-physical address translations. For example, in a processor implemented in the x86 architecture, with paging enabled a paging mechanism within the processor translates a virtual or “linear” address to a physical address. If an accessed page is not located within the system memory, paging support constructs (e.g., operating system software) load the accessed page from secondary memory (e.g., disk drive) into system memory. In some x86 processors, a set of hierarchical translation tables or “page tables,” stored within the system memory, are used to store information needed by the paging mechanism to perform the virtual-to-physical address translations.
Since accesses to the system memory require relatively large amounts of time, address translations may be a source of processing latency. To reduce the number of required system memory accesses to retrieve information from page tables, a small cache memory system called a translation lookaside buffer (TLB) is typically used to store the most recently used address translations. Typically, translations are provided on a page basis (e.g. 4 kilobytes, 2 megabytes, etc.) and the TLB may store the page portion of the virtual address and the page portion of the corresponding physical address. The TLB may then be searched for the issued virtual address. If found, a physical address corresponding to the issued virtual address may then be used to access system memory. As the amount of time required to access an address translation in the TLB is relatively small, overall processor performance may be increased as needed address translations are often found in the readily accessible TLB.
Despite the advantages provided by a TLB, there may still be drawbacks. Some processor microarchitectures, such as in a superscalar processor, for example, may include multiple pipelines. To obtain high performance from such designs, low latency access to relatively large TLB structures may be desirable. To provide the low latency to the multiple pipelines, some conventional TLB structures may include several large multiported structures. In addition, multiple page sizes may be supported, and each TLB structure may support a different page size. Alternatively, very large fully associative TLB structures may support multiple page sizes. However, such conventional TLB designs may not only take up considerable area on the integrated circuit and have higher access times, but they may also consume an unacceptable amount of power.